100314
Low Power Quint Differential Line Receiver

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The 100314 is a monolithic quint differential line receiver with emitter-follower outputs. An internal reference supply (VBB) is available for single-ended reception. When used in single-ended operation the apparent input threshold of the true inputs is 25 mV to 30 mV higher (positive) than the threshold of the complementary inputs. Unlike other F100K ECL devices, the inputs do not have input pull-down resis- tors.

Active current sources provide common-mode rejection of 1.0V in either the positive or negative direction. A defined output state exists if both inverting and non-inverting inputs are at the same potential between VEE and VCC. The defined state is logic HIGH on the Oa–Oe outputs.
 

Storage Temperature (TSTG)                            −65°C to +150°C
Maximum Junction Temperature (TJ)                                 +150°C
Pin Potential to Ground Pin (VEE)                          −7.0V to +0.5V
Input Voltage (DC)                                                    VEE to +0.5V
Output Current (DC Output HIGH)                                   −50 mA
ESD (Note 2)                                                                    ≥2000V
● 35% power reduction of the 100114
2000V ESD protection
Pin/function compatible with 100114
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range (PLCC package only)

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Datasheet

Size: 81.96KB
Page: 7
PDF: 100314.pdf
  • Description:
    Low Power Quint Differential Line Receiver
  • MFG:
    FAIRCHILD [Fairchild Semiconductor]
 

Abstract


? 2000 Fairchild Semiconductor Corporation DS010260 www.fairchildsemi.com
February 1990
Revised August 2000
1
00314 Low
Power Quint

Di
ff
erent
i
a
l
Line Recei
ver
100314
Low Power Quint Differential Line Receiver
General Description
The 100314 is a monolithic quint differential line receiver
with emitter-follower outputs. An internal reference supply
(V
BB
) is available for single-ended reception. When used in
single-ended operation the apparent input threshold of the
true inputs is 25 mV to 30 mV higher (positive) than the
threshold of the complementary inputs. Unlike other F100K
ECL devices, the inputs do not have input pull-down resis-
tors.
Active current sources provide common-mode rejection of
1.0V in either the positive or negative direction. A defined
output state exists if both inverting and non-inverting inputs
are at the same potential between V
EE
and V
CC
. The
defined state is logic HIGH on the O
a
–O
e
outputs.
Features
a73 35% power reduction of the 100114
a73 2000V ESD protection
a73 Pin/function compatible with 100114
a73 Voltage compensated operating range = ?4.2V to ?5.7V
a73 Available to industrial grade temperature range
(PLCC package only)

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
100314SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100314PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100314QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100314QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (?40°C to +85°C)
Pin Names Description
D
a
–D
e
Data Inputs
D
a
–D
e
Inverting Data Inputs
O
a
–O
e
Data Outputs
O
a
–O
e
Complementary Data Outputs

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