74LCX16652
Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs

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   The LCX16652 contains sixteen non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA ) are provided to control the transceiver function (see Functional Description).

   The LCX16652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment.

   The LCX16652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Symbol Parameter Value Conditions Units
VCC Supply Voltage −0.5 to +7.0   V
VI DC Input Voltage
−0.5 to +7.0   V
VO DC Output Voltage −0.5 to +7.0
−0.5 to VCC +0.5
Output in3-STATE
Output in HIGH or LOW State (Note4)
V
 
IIK DC Input Diode Current
−50 VI < GND mA
IOK DC Output Diode Current
−50
+50
VO < GND
VO > VCC
mA
IO DC Output Source/Sink Current ±50   mA
ICC DC Supply Current per Supply Pin ±100   mA
IGND DC Ground Current per Ground Pin ±100   mA
TSTG Storage Temperature −65 to +150   °C
● 5V tolerant inputs and outputs
● 2.3V–3.6V VCC specifications provided
● 5.7 ns tPD max (VCC = 3.3V), 20 mA ICC max
● Power down high impedance inputs and outputs
● Supports live insertion/withdrawal (Note 1)
● ±24 mA output drive (VCC = 3.0V)
● Implements patented noise/EMI reduction circuitry
● Latch-up performance exceeds 500 mA
● ESD performance:
  Human body model > 2000V
  Machine model > 200V

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Datasheet

Size: 93.61KB
Page: 10
PDF: 74LCX16652.pdf
  • Description:
    Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
  • MFG:
    FAIRCHILD [Fairchild Semiconductor]
 

Abstract


February 1994
Revised April 1999
7
4LCX16652 Low
V
o
lt
age T
r
ansce
iver
/Regi
ster

wi
th 5V
T
o
l
e
rant
Input
s
a
nd
Out
puts
? 1999 Fairchild Semiconductor Corporation DS012005.prf www.fairchildsemi.com
74LCX16652
Low Voltage Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX16652 contains sixteen non-inverting bidirectional
bus transceivers with 3-STATE outputs providing multi-
plexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Output Enable pins (OEAB, OEBA)
are provided to control the transceiver function (see Func-
tional Description).
The LCX16652 is designed for low-voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
a73 5V tolerant inputs and outputs
a73 2.3V–3.6V V
CC
specifications provided
a73 5.7 ns t
PD
max (V
CC
= 3.3V), 20 ?A I
CC
max
a73 Power down high impedance inputs and outputs
a73 Supports live insertion/withdrawal (Note 1)
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74LCX16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0
–A
15
Data Register A Inputs/3-STATE Outputs
B
0
–B
15
Data Register B Inputs/3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OEAB
n
, OEBA
n
Output Enable Inputs

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