CY7C1049
512K x 8 Static RAM

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The CY7C1049 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................. –65°C to +150°C
Ambient Temperature with
Power Applied......................................... –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ..................................–0.5V to VCC + 0.5V
DC Input Voltage[1]...............................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
• High speed
   —tAA = 15 ns
• Low active power
   —1210 mW (max.)
• Low CMOS standby power (Commercial L version)
   —2.75 mW (max.)
• 2.0V Data Retention (400 mW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features

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Datasheet

Size: 128.52KB
Page: 10
PDF: CY7C1049.pdf
  • Description:
    512K x 8 Static RAM
  • MFG:
    CYPRESS [Cypress Semiconductor]
 

Abstract


PRELIMINARY
512K x 8 Static RAM
CY7C1049

Cypress Semiconductor Corporation ? 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-05063 Rev. ** Revised August 31, 2001
049
Features
? High speed
—t
AA
= 15 ns
Low active power
— 1210 mW (max.)
Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
2.0V Data Retention (400 ?W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
18
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
14 15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODE
R
SENS
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
1049–1
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
1049–2
A
9
A
18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A
10
Selection Guide
7C1049-12 7C1049-15 7C1049-17 7C1049-20 7C1049-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) 240 220 195 185 180
Maximum CMOS Standby
Current (mA)
Com’l 888 8 8
Com’l L 0.5 0.5 0.5 0.5 0.5
Ind’l 999 9 9
Military 10 10
Shaded areas contain advance information.

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