HDMP-1636A
Gigabit Ethernet and Fibre Channel SerDes ICs

Part Number:
Quantity:
Country/Region:
Email:
Description:
Code:
For complete your requirements, please fill in the part number,quantity and other contact details. So that more suppliers will contact you.
  Supplier Information Part Number Mfg Pack D/C Description Inquire

The HDMP-1636A/46A/T1636A transceiver is a single integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet, 1062.5 MBd Fibre Channel, and proprietary link interfaces. It provides complete Serialize/ Deserialize (SerDes) for copper transmission, incorporating the Gigabit Ethernet/Fibre Channel transmit and receive functions into a single device.

This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification.

The transmitter section accepts 10-bit wide parallel TTL data and serializes this data into a high speed serial data stream. The parallel data is expected to be “8B/10B” encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the reference clock (used as the transmit byte clock). A 1062.5 MHz reference clock is used in Fibre Channel operation, whereas a 125 MHz reference clock is used in Gigabit Ethernet operation.

The transmitter section’s PLL locks to the user supplied reference byte clock. This clock is then multiplied by 10 to generate the high speed serial clock used to generate the high speed output. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.

The receiver section accepts a serial electrical data stream at 1062.5 MBd or 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment.
• 1250 MBd Gigabit Ethernet Interface
• 1062.5 MBd Fibre Channel Interface
• Mass Storage System I/O Channel
• Work Station/Server I/O Channel
• Backplane Serialization
• FC Interface for Disk Drives and Arrays
Symbol Parameter Units Min. Max.
VCC Supply Voltage V -0.5 5.0
VIN,TTL TTL Input Voltage V -0.7 VCC +2.8
VIN,HS_IN HS_IN Input Voltage V VCC
IO,TTL TTL Output Source Current mA 13
Tstg Storage Temperature °C –65 +150
Tj Junction Operating Temperature °C 0 +150
• IEEE 802.3z Gigabit Ethernet Compatible
• ANSI x3.230-1994 Fibre Channel Compatible (FC-O)
• Supports Serial Data Rates of 1062.5 MBd (Fibre Channel) & 1250 MBd (Gigabit Ethernet)
• Low Power Consumption, 630 mW Typical
• Transmitter and Receiver Functions Incorporated onto a Single IC
• Three Package Sizes Available:
– 10 mm TQFP (HDMP-T1636A)
– 10 mm PQFP (HDMP-1636A)
– 14 mm PQFP (HDMP-1646A)
• 10-Bit Wide Parallel TTL Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 kV ESD Protection on All Pins

HDM1002AD HDM1003AD Tantalum Capacitors
HDM-1210BD HDM300-19 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM
HDM300-19/6 UProcessor Supervisory HDM300-28/4
HDM30-12D-S24 8-AMPERE N-P-N DARLINGTON POWER TRANSISTORS HDM8513 DVB/DSS Compliant Receiver
HDM8515 DVB/DSS Compliant Receiver HDMB200-5 CMOS ASYNCHRONOUS FIFO
HDMD-1034 UNI-DIRECTIONAL GLASS PASSIVATED JUNCTION TRANSIENT VOLTAGE SUPPRESSOR 1500 WATTS, 5.0 THRU 170 VOLTS HDMI-19-01-F-SM 8-Bit CMOS Microcontrollers with A/D Converter
HDMIULC6-4SC6 Ultra large bandwidth ESD protection HDMJ08-1 Advanced Single or Dual Cell Lithium-Ion/ Lithium-Polymer Charge Management Controllers
HDMMBT2222ALT1 PWM Controlled, PWM/PFM Switchable Step-Up DC/DC Controllers HDMP-0241 128M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY
HDMP-0421 Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions HDMP-0421G SMART 3 ADVANCED BOOT BLOCK WORD-WIDE
HDMP-0422 Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops HDMP-0422GR1

Datasheet

Size: 281.64KB
Page: 18
PDF: HDMP-1636A.pdf
  • Description:
    Gigabit Ethernet and Fibre Channel SerDes ICs
  • MFG:
    HP [Agilent(Hewlett-Packard)]
 

Abstract


HDMP-1636A Transceiver
HDMP-1646A Transceiver
HDMP-T1636A Transceiver
Features
? IEEE 802.3z Gigabit Ethernet
Compatible
? ANSI x3.230-1994 Fibre
Channel Compatible (FC-O)
? Supports Serial Data Rates of
1062.5 MBd (Fibre Channel)
& 1250 MBd (Gigabit
Ethernet)
? Low Power Consumption,
630 mW Typical
? Transmitter and Receiver
Functions Incorporated onto
a Single IC
? Three Package Sizes
Available:
– 10 mm TQFP (HDMP-T1636A)
– 10 mm PQFP (HDMP-1636A)
– 14 mm PQFP (HDMP-1646A)
? 10-Bit Wide Parallel TTL
Compatible I/Os
? Single +3.3 V Power Supply
? 5-Volt Tolerant I/Os
? 2 kV ESD Protection on All
Pins
Applications
? 1250 MBd Gigabit Ethernet
Interface
? 1062.5 MBd Fibre Channel
Interface
? Mass Storage System I/O
Channel
? Work Station/Server I/O
Channel
? Backplane Serialization
? FC Interface for Disk Drives
and Arrays
Gigabit Ethernet and
Fibre Channel SerDes ICs
Technical Data
Description
The HDMP-1636A/46A/T1636A
transceiver is a single integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet,
1062.5 MBd Fibre Channel, and
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating the
Gigabit Ethernet/Fibre Channel
transmit and receive functions
into a single device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the reference clock (used
as the transmit byte clock). A
1062.5 MHz reference clock is
used in Fibre Channel operation,
whereas a 125 MHz reference
clock is used in Gigabit Ethernet
operation.
The transmitter section’s PLL
locks to the user supplied
reference byte clock. This clock
is then multiplied by 10 to gener-
ate the high speed serial clock
used to generate the high speed
output. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd or 1250 MBd and
recovers the original 10-bit wide
parallel data. The receiver PLL
locks onto the incoming serial
signal and recovers the high
speed serial clock and data. The
serial data is converted back into
10-bit parallel data, recognizing
the 8B/10B comma character to
establish byte alignment.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).

Stock Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  All  
About Us  |  Contact us   |  Map  |  Link   |  Custom PCB Prototype Manufacturer
© 2008-2011 TradeOfic.com Corp.All Rights Reserved.